Mark x86's memory barrier inline assembly as clobbering the cpu flags.

x86's memory barrier assembly was marked as clobbering "memory" but
not "cc" even though 'addl' sets various flags. As it turns out gcc on
x86 implicitly assumes "cc" on every inline assembler statement, so
it's not a bug. But as that's poorly documented and might get copied
to architectures or compilers where that's not the case, it seems
better to be precise.

Discussion: 20140919100016.GH4277@alap3.anarazel.de

To keep the code common, backpatch to 9.2 where explicit memory
barriers were introduced.

diff --git a/src/include/storage/barrier.h b/src/include/storage/barrier.h
index 1b35bb2c7b721fff597cf04bb283457a2c821b55..de7ffdefb92aa67e6f779fbcf1403fe0f12c4a58 100644 (file)
--- a/src/include/storage/barrier.h
+++ b/src/include/storage/barrier.h
@@ -70,7 +70,7 @@ extern slock_t dummy_spinlock;
  * "lock; addl" has worked for longer than "mfence".
  */
 #define pg_memory_barrier()        \
-   __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
+   __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory", "cc")
 #define pg_read_barrier()      pg_compiler_barrier()
 #define pg_write_barrier()     pg_compiler_barrier()
 #elif defined(__x86_64__)      /* 64 bit x86 */
@@ -84,7 +84,7 @@ extern slock_t dummy_spinlock;
  * do those things, a compiler barrier should be enough.
  */
 #define pg_memory_barrier()        \
-   __asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory")
+   __asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory", "cc")
 #define pg_read_barrier()      pg_compiler_barrier()
 #define pg_write_barrier()     pg_compiler_barrier()
 #elif defined(__ia64__) || defined(__ia64)