PCI Firmware Specification
Revision 3.0
June 20, 2005
PCI FIRMWARE SPECIFICATION, REV. 3.0
2
Revision Revision History Date
1.0 Original issue distributed by Intel Corporation 9/28/1992
2.0 Updated to be in synch with PCI Bus Specification, Rev. 2.0 7/20/1993
2.1 Added functions for PCI IRQ routing; clarifications. 8/26/1994
3.0
Updated revision evolving the specification to include all
aspects of PCI and system firmware.
6/20/2005
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contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
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Questions regarding the PCI Firmware Specification or membership in PCI-SIG may be forwarded
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visit: http://www.pcisig.com/developers/technical_support.
DISCLAIMER
This PCI Firmware Specification is provided “as is” with no warranties whatsoever,
including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of
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to any intellectual property rights is granted herein.
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owners.
Copyright © 1992-2005 PCI-SIG
PCI FIRMWARE SPECIFICATION, REV. 3.0
3
Contents
1. INTRODUCTION..................................................................................................................7
1.1. S
COPE .............................................................................................................................. 7
1.2. REFERENCE DOCUMENTS................................................................................................. 7
1.3. T
ERMS AND ACRONYMS .................................................................................................. 8
2. TRADITIONAL PCI BIOS ................................................................................................11
2.1. F
UNCTIONAL DESCRIPTION............................................................................................ 11
2.2. ASSUMPTIONS AND CONSTRAINTS ................................................................................. 11
2.2.1. ROM BIOS Location............................................................................................... 11
2.2.2. Calling Conventions................................................................................................ 11
2.2.3. Interrupt Support .................................................................................................... 12
2.3. BIOS32 SERVICE DIRECTORY ....................................................................................... 12
2.3.1. Determining the Existence of BIOS32 Service Directory....................................... 12
2.3.2. Calling Interface for BIOS32 Service Directory .................................................... 13
2.4. PCI BIOS 32-BIT SERVICE............................................................................................. 14
2.5. HOST INTERFACE ........................................................................................................... 15
2.5.1. Identifying PCI Resources ...................................................................................... 15
2.5.2. PCI BIOS Present ................................................................................................... 15
2.5.3. Find PCI Device ..................................................................................................... 17
2.5.4. Find PCI Class Code .............................................................................................. 18
2.6. PCI SUPPORT FUNCTIONS .............................................................................................. 19
2.6.1. Generate Special Cycle........................................................................................... 19
2.6.2. Get PCI Interrupt Routing Expansions................................................................... 19
2.6.3. Set PCI Hardware Interrupt ................................................................................... 22
2.7. ACCESSING CONFIGURATION SPACE.............................................................................. 24
2.7.1. Access Rules for PCI Express I/O and Memory Mapped Accesses........................ 24
2.7.2. INT1Ah Access Calls in Real Mode........................................................................ 25
2.7.3. Read Configuration Byte......................................................................................... 25
2.7.4. Read Configuration Word....................................................................................... 26
2.7.5. Read Configuration DWORD ................................................................................. 27
2.7.6. Write Configuration Byte........................................................................................ 28
2.7.7. Write Configuration Word...................................................................................... 29
2.7.8. Write Configuration DWORD................................................................................. 30
2.8. F
UNCTION LIST .............................................................................................................. 31
2.9. RETURN CODE LIST ....................................................................................................... 32
3. EFI PCI SERVICES............................................................................................................33
3.1. EFI
DRIVER MODEL....................................................................................................... 33
3.1.1. PCI Root Bridge Protocol....................................................................................... 33
3.1.2. PCI Driver Model ................................................................................................... 34
3.2. PCI-X
MODE 2 AND PCI EXPRESS................................................................................. 34
3.3. EFI
BYTE CODE............................................................................................................. 34
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3.4. UNIVERSAL GRAPHICS ADAPTER................................................................................... 34
3.5. DEVICE STATE AT FIRMWARE/OPERATING SYSTEM HANDOFF ...................................... 35
4. PCI SERVICES IN ACPI ...................................................................................................39
4.1. E
NHANCED CONFIGURATION ACCESS METHOD BASE ADDRESS.................................... 39
4.1.1. Background............................................................................................................. 40
4.1.2. MCFG Table Description ....................................................................................... 41
4.1.3. The _CBA Method................................................................................................... 43
4.1.4. System Software Implication of MCFG and _CBA................................................. 45
4.1.5. Plug-and-Play ID Defined for Enhanced Configuration Space Access Capable
Devices 46
4.2. M
ECHANISM FOR CONTROLLING SYSTEM WAKE FROM PCI EXPRESS........................... 47
4.3. PCI ROOT BRIDGE DESCRIPTION ................................................................................... 47
4.3.1. Identification........................................................................................................... 47
4.3.2. Resource Description.............................................................................................. 48
4.3.2.1. Resource Setting ............................................................................................... 48
4.3.2.2. Boot Bus Number ............................................................................................. 48
4.3.2.3. PCI Segment Group.......................................................................................... 48
4.4. PCI INTERRUPT ROUTING .............................................................................................. 48
4.5. _OSC – A MECHANISM FOR EXPOSING PCI EXPRESS CAPABILITIES SUPPORTED BY AN
OPERATING SYSTEM .................................................................................................................. 49
4.5.1. _OSC Interface for PCI Host Bridge Devices ........................................................ 49
4.5.2. Rules for Evaluating _OSC..................................................................................... 53
4.5.2.1. Query Flag ........................................................................................................ 53
4.5.2.2. Evaluation Conditions....................................................................................... 53
4.5.2.3. Sequence of _OSC Calls................................................................................... 53
4.5.2.4. Dependencies Between _OSC Control Bits...................................................... 54
4.5.3. ASL Example........................................................................................................... 54
4.6. _DSM DEFINITIONS FOR PCI......................................................................................... 56
4.6.1. _DSM for PCI Express Slot Information................................................................ 56
4.6.2. _DSM for PCI Express Slot Number ...................................................................... 58
4.6.3. _DSM for Vendor-specific Token ID Strings.......................................................... 60
4.6.4. _DSM for PCI Bus Capabilities.............................................................................. 61
4.6.4.1. Bus Capabilities Structure................................................................................. 62
4.6.4.1.1. Bus Types...............................................................................................................62
4.6.4.1.2. Bus Capabilities Structure Definitions...................................................................62
4.6.4.1.3. _DSM for Bus Capabilities ....................................................................................63
4.7. G
ENERIC ACPI PCI SLOT DESCRIPTION ........................................................................ 65
4.8. T
HE OSHP CONTROL METHOD ..................................................................................... 65
4.9. HOT PLUG PARAMETERS................................................................................................ 67
4.9.1. _HPP....................................................................................................................... 67
4.9.2. _HPX....................................................................................................................... 67
4.9.3. Device State During Hot Plug ................................................................................ 67
4.9.4. Slot Power State After Device Removal.................................................................. 67
5. PCI EXPANSION ROMS...................................................................................................69
5.1. PCI EXPANSION ROM CONTENTS ................................................................................. 69
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5.1.1. PCI Expansion ROM Header Format..................................................................... 70
5.1.2. PCI Data Structure Format .................................................................................... 71
5.1.3. Device List Format ................................................................................................. 73
5.2. F
IRMWARE POWER-ON SELF TEST (POST) FIRMWARE.................................................. 74
5.2.1. PC-compatible Expansion ROMs (Code Type 0) ................................................... 76
5.2.1.1. Expansion ROM Header Extensions ................................................................ 77
5.2.1.2. POST Firmware Extensions.............................................................................. 77
5.2.1.3. Resizing of Expansion ROMs During INIT ..................................................... 78
5.2.1.3.1. Calculating a New Checksum at the End of INIT..................................................79
5.2.1.4. Image Structure and Length.............................................................................. 79
5.2.1.5. Memory Usage.................................................................................................. 79
5.2.1.6. Verification of BIOS Support........................................................................... 80
5.2.1.7. Permanent Memory........................................................................................... 80
5.2.1.8. Temporary Memory.......................................................................................... 81
5.2.1.9. Memory Locations............................................................................................ 81
5.2.1.10. Permanent Memory Size Limits ..................................................................... 81
5.2.1.11. Multiple Requests for Memory....................................................................... 82
5.2.1.12. Protected Mode............................................................................................... 82
5.2.1.13. Run-Time Expansion ROM Size.................................................................... 82
5.2.1.14. Relocation of Expansion ROM Run-time Code ............................................. 82
5.2.1.15. Expansion ROM Placement Address.............................................................. 83
5.2.1.16. VGA Expansion ROM.................................................................................... 84
5.2.1.17. Expansion ROM Placement Alignment.......................................................... 84
5.2.1.18. BIOS Boot Specification................................................................................. 84
5.2.1.19. Extended BIOS Data Area (EBDA) Usage .................................................... 84
5.2.1.20. POST Memory Manager (PMM) Functions................................................... 86
5.2.1.21. Backward Compatibility of Option ROMs..................................................... 86
5.2.1.22. Option ROM and IRET Handling................................................................... 87
5.2.1.23. Stack Size Requirement by Expansion ROM................................................. 87
5.2.1.24. Configuration Code for Expansion ROMs ..................................................... 87
5.2.1.24.1. Executing the Expansion ROM Configuration Code...........................................89
5.2.1.24.2. Configuration Utility Behavior Under Console Redirection................................90
5.2.1.24.3. Configuration Utility Code Header......................................................................90
5.2.1.25. DMTF Command Line Protocol (CLP) Support............................................ 91
5.2.2. EFI Expansion ROM (Type 3) ................................................................................ 92
6. PCI SERVICES SPECIFIC TO DIG64-COMPLIANT SYSTEMS..............................93
