
Copyright © 2009 ARM Limited. All rights reserved.
ARM DUI 0497A (ID112109)
Cortex
™
-M0 Devices
Generic User Guide

ii Copyright © 2009 ARM Limited. All rights reserved. ARM DUI 0497A
Non-Confidential, Unrestricted Access ID112109
Cortex-M0 Devices
Generic User Guide
Copyright © 2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM
®
Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change History
Date Issue Confidentiality Change
08 October 2009 A Non-Confidential, Unrestricted Access First release

ARM DUI 0497A Copyright © 2009 ARM Limited. All rights reserved. iii
ID112109 Non-Confidential, Unrestricted Access
Contents
Cortex-M0 Devices Generic User Guide
Preface
About this book ............................................................................................ viii
Feedback ....................................................................................................... xi
Chapter 1 Introduction
1.1 About the Cortex-M0 processor and core peripherals ................................ 1-2
Chapter 2 The Cortex-M0 Processor
2.1 Programmers model .................................................................................... 2-2
2.2 Memory model .......................................................................................... 2-12
2.3 Exception model ....................................................................................... 2-19
2.4 Fault handling ........................................................................................... 2-27
2.5 Power management .................................................................................. 2-28
Chapter 3 The Cortex-M0 Instruction Set
3.1 Instruction set summary .............................................................................. 3-2
3.2 Intrinsic functions ........................................................................................ 3-5
3.3 About the instruction descriptions ............................................................... 3-7
3.4 Memory access instructions ...................................................................... 3-16
3.5 General data processing instructions ........................................................ 3-27
3.6 Branch and control instructions ................................................................. 3-45
3.7 Miscellaneous instructions ........................................................................ 3-48

Contents
iv Copyright © 2009 ARM Limited. All rights reserved. ARM DUI 0497A
Non-Confidential, Unrestricted Access ID112109
Chapter 4 Cortex-M0 Peripherals
4.1 About the Cortex-M0 peripherals ................................................................ 4-2
4.2 Nested Vectored Interrupt Controller .......................................................... 4-3
4.3 System Control Block ............................................................................... 4-11
4.4 Optional system timer, SysTick ................................................................ 4-21
Appendix A Cortex-M0 Options
A.1 Cortex-M0 implementation options ............................................................. A-2
Glossary

ARM DUI 0497A Copyright © 2009 ARM Limited. All rights reserved. v
ID112109 Non-Confidential, Unrestricted Access
List of Tables
Cortex-M0 Devices Generic User Guide
Change History ............................................................................................................. ii
Table 2-1 Summary of processor mode and stack use options ................................................ 2-2
Table 2-2 Core register set summary ........................................................................................ 2-3
Table 2-3 PSR register combinations ........................................................................................ 2-5
Table 2-4 APSR bit assignments .............................................................................................. 2-6
Table 2-5 IPSR bit assignments ................................................................................................ 2-7
Table 2-6 EPSR bit assignments .............................................................................................. 2-8
Table 2-7 PRIMASK register bit assignments ........................................................................... 2-9
Table 2-8 CONTROL register bit assignments .......................................................................... 2-9
Table 2-9 Memory access behavior ........................................................................................ 2-15
Table 2-10 Memory region shareability and cache policies ...................................................... 2-15
Table 2-11 Properties of the different exception types .............................................................. 2-20
Table 2-12 Exception return behavior ....................................................................................... 2-26
Table 3-1 Cortex-M0 instructions .............................................................................................. 3-2
Table 3-2 CMSIS intrinsic functions to generate some Cortex-M0 instructions ........................ 3-5
Table 3-3 CMSIS intrinsic functions to access the special registers ......................................... 3-6
Table 3-4 Condition code suffixes ........................................................................................... 3-15
Table 3-5 Memory access instructions .................................................................................... 3-16
Table 3-6 Data processing instructions ................................................................................... 3-27
Table 3-7 ADC, ADD, RSB, SBC and SUB operand restrictions ............................................ 3-31
Table 3-8 Branch and control instructions ............................................................................... 3-45
Table 3-9 Branch ranges ......................................................................................................... 3-46
Table 3-10 Miscellaneous instructions ...................................................................................... 3-48