SDC命令详解：使用update_timing命令进行更新

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已于 2025-04-24 18:24:47 修改

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分类专栏： SDC命令详解文章标签：数字IC SDC命令

于 2025-04-03 01:47:37 首次发布

本文链接：https://blog.csdn.net/weixin_45791458/article/details/146887600

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update_timing命令用于更新当前设计的时序信息，当设计出现设置变更时，时序信息会变得过时，此时该命令用于在这些变化发生后进行显式更新（其实它并不是一个SDC命令，归为此类只是为了方便管理）。

一般情况

在大多数情况下，当使用综合类命令(compile、compile_ultra)或显示时序信息的报告类命令（report_timing、report_port）时，时序信息会自动更新（即执行一个隐式的update_timing命令），如例1所示。其中"Information: Updating design information... (UID-85)"表明进行了时序更新（这里为隐式更新）。

// 例1
dc_shell> set_load 0.1 [get_ports data_out]
dc_shell> report_port
Information: Updating design information... (UID-85)
 
****************************************
Report : port
Design : logic_circuit
Version: W-2024.09-SP2
Date   : Wed Apr  2 18:31:07 2025
****************************************


                       Pin      Wire     Max     Max     Connection
Port           Dir     Load     Load     Trans   Cap     Class      Attrs
--------------------------------------------------------------------------------
clk1           in      0.0000   0.0000   --      --      --         
clk2           in      0.0000   0.0000   --      --      --         
data_in        in      0.0000   0.0000   --      --      --         
rst_n          in      0.0000   0.0000   --      --      --         
data_out       out     0.1000   0.0000   --      --      --

手动指定update_timing命令也是可行的，如例2所示。其中"Information: Updating design information... (UID-85)"表明进行了时序更新（这里为显式更新）。

// 例2
dc_shell> create_clock -period 10 [get_ports clk1]
dc_shell> update_timing
Information: Updating design information... (UID-85)
dc_shell> report_clock
****************************************
Report : clocks
Design : logic_circuit
Version: W-2024.09-SP2
Date   : Wed Apr  2 18:50:32 2025
****************************************

Attributes:
    d - dont_touch_network
    f - fix_hold
    p - propagated_clock
    G - generated_clock
    g - lib_generated_clock

Clock          Period   Waveform            Attrs     Sources
--------------------------------------------------------------------------------
clk1            10.00   {0 5}                         {clk1}
--------------------------------------------------------------------------------

PrimeTime中的特殊情况

某些信息可能对于更新的要求更高，比如端口的ideal_network属性在使用set_ideal_network命令设置后无法直接由report_port命令查看，需要使用update_timing、report_ideal_network或report_timing命令后才能更新，如例3所示。

// 例3
pt_shell> set_ideal_network [get_ports d]
pt_shell> report_port
****************************************
Report : port
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 00:57:30 2025
****************************************

Attributes:
    I - ideal network
    H - HyperScale context override

                          Pin Cap         Wire Cap
Port           Dir        min/max         min/max     Attributes
-------------------------------------------------------------------
clk            in      0.0000/0.0000   0.0000/0.0000  
d              in      0.0000/0.0000   0.0000/0.0000  
enable         in      0.0000/0.0000   0.0000/0.0000  
o              out     0.0000/0.0000   0.0000/0.0000  
rst_n          in      0.0000/0.0000   0.0000/0.0000  
pt_shell> update_timing  // report_ideal_network或report_timing命令也可
pt_shell> report_port
****************************************
Report : port
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 00:57:47 2025
****************************************

Attributes:
    I - ideal network
    H - HyperScale context override

                          Pin Cap         Wire Cap
Port           Dir        min/max         min/max     Attributes
-------------------------------------------------------------------
clk            in      0.0000/0.0000   0.0000/0.0000  
d              in      0.0000/0.0000   0.0000/0.0000  I
enable         in      0.0000/0.0000   0.0000/0.0000  
o              out     0.0000/0.0000   0.0000/0.0000  
rst_n          in      0.0000/0.0000   0.0000/0.0000

类似的情况还发生在生成时钟的waveform中，在使用create_generated_clock命令创建后无法直接由report_clock命令查看，需要使用update_timing或report_timing命令后才能更新，如例4所示。

// 例4
pt_shell> create_clock -period 10 [get_ports clk]
pt_shell> create_generated_clock -divide_by 1 -source [get_ports clk] [get_pins u5/Q]
pt_shell> report_clock
****************************************
Report : clock
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 01:06:29 2025
****************************************

Attributes:
    p - Propagated clock
    G - Generated  clock
    I - Inactive   clock

Clock             Period          Waveform            Attrs     Sources
-----------------------------------------------------------------------
clk                10.00          {0 5}                         {clk}



Generated     Master          Generated       Master          Waveform
Clock         Source          Source          Clock           Modification
-------------------------------------------------------------------------------
u5/Q          clk             u5/Q            *               div(1)
pt_shell> update_timing  // report_timing命令也可
pt_shell> report_clock
****************************************
Report : clock
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 01:06:42 2025
****************************************

Attributes:
    p - Propagated clock
    G - Generated  clock
    I - Inactive   clock

Clock             Period          Waveform            Attrs     Sources
-----------------------------------------------------------------------
clk                10.00          {0 5}                         {clk}
u5/Q               10.00          {0 5}               G         {u5/Q}



Generated     Master          Generated       Master          Waveform
Clock         Source          Source          Clock           Modification
-------------------------------------------------------------------------------
u5/Q          clk             u5/Q            clk             div(1)

更为特殊的情况

该情况涉及到时钟共同悲观路径移除，更详细的信息可以在下面的博客中找到。

静态时序分析：时钟共同悲观路径(CPPR)移除与重汇聚悲观路径移除(CRPR)https://blog.csdn.net/weixin_45791458/article/details/146310748?spm=1001.2014.3001.5501 timing_clock_reconvergence_pessimism变量用于控制如何计算时钟悲观路径去除的值，允许的值为normal（默认值）和same_transition，当在这两者之间进行切换时，需要使用update_timing命令或者关开timing_remove_clock_reconvergence_pessimism变量并使用report_timing命令才能更新（只使用report_timing命令无法更新悲观路径的计算），如例5所示。

// 例5
dc_shell> create_clock -period 10 [get_ports clk]
dc_shell> set_propagated_clock [get_clocks clk]
dc_shell> set_operating_condition -analysis_type on_chip_variation fast
dc_shell> set_input_transition -max 0.8 [get_port clk]
dc_shell> set_input_transition -min 0.1 [get_port clk]
dc_shell> set_app_var timing_remove_clock_reconvergence_pessimism true
dc_shell> report_timing -path_type full_clock -transition_time -significant_digits 7 
****************************************
Report : timing
        -path full_clock
        -delay max
        -max_paths 1
        -transition_time
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 01:41:19 2025
****************************************

Operating Conditions: fast   Library: fast
Wire Load Model Mode: top

  Startpoint: q_reg (rising edge-triggered flip-flop clocked by clk)
  Endpoint: o_reg (rising edge-triggered flip-flop clocked by clk')
  Path Group: clk
  Path Type: max

  Point                         Trans      Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                0.0000000  0.0000000
  clk (in)                   0.8000000 0.0000000  0.0000000 r
  u1/Y (CLKBUFX1)            0.0446310 0.0500520  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/Q (DFFRQX2)          0.0173597 0.0859217  0.1359738 r
  o_reg/D (DFFRQX2)          0.0173597 0.0000000  0.1359738 r
  data arrival time                               0.1359738

  clock clk' (rise edge)               5.0000000  5.0000000
  clk (in)                   0.1000000 0.0000000  5.0000000 f
  u1/Y (CLKBUFX1)            0.0234806 0.0424690  5.0424690 f
  U4/Y (CLKINVX1)            0.0144704 0.0131054  5.0555744 r
  o_reg/CK (DFFRQX2)         0.0144704 0.0000000  5.0555744 r
  clock reconvergence pessimism        0.0136884  5.0692630
  o_reg/CK (DFFRQX2)                   0.0000000  5.0692630 r
  library setup time                   -0.0434659 5.0257969
  data required time                              5.0257969
  -----------------------------------------------------------
  data required time                              5.0257969
  data arrival time                               -0.1359738
  -----------------------------------------------------------
  slack (MET)                                     4.8898230
dc_shell> set_app_var timing_clock_reconvergence_pessimism same_transition
dc_shell> report_timing -path_type full_clock -transition_time -significant_digits 7
****************************************
Report : timing
        -path full_clock
        -delay max
        -max_paths 1
        -transition_time
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 01:41:32 2025
****************************************

Operating Conditions: fast   Library: fast
Wire Load Model Mode: top

  Startpoint: q_reg (rising edge-triggered flip-flop clocked by clk)
  Endpoint: o_reg (rising edge-triggered flip-flop clocked by clk')
  Path Group: clk
  Path Type: max

  Point                         Trans      Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                0.0000000  0.0000000
  clk (in)                   0.8000000 0.0000000  0.0000000 r
  u1/Y (CLKBUFX1)            0.0446310 0.0500520  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/Q (DFFRQX2)          0.0173597 0.0859217  0.1359738 r
  o_reg/D (DFFRQX2)          0.0173597 0.0000000  0.1359738 r
  data arrival time                               0.1359738

  clock clk' (rise edge)               5.0000000  5.0000000
  clk (in)                   0.1000000 0.0000000  5.0000000 f
  u1/Y (CLKBUFX1)            0.0234806 0.0424690  5.0424690 f
  U4/Y (CLKINVX1)            0.0144704 0.0131054  5.0555744 r
  o_reg/CK (DFFRQX2)         0.0144704 0.0000000  5.0555744 r
  clock reconvergence pessimism        0.0136884  5.0692630
  o_reg/CK (DFFRQX2)                   0.0000000  5.0692630 r
  library setup time                   -0.0434659 5.0257969
  data required time                              5.0257969
  -----------------------------------------------------------
  data required time                              5.0257969
  data arrival time                               -0.1359738
  -----------------------------------------------------------
  slack (MET)                                     4.8898230
dc_shell> update_timing // 关开timing_remove_clock_reconvergence_pessimism变量并使用report_timing命令也可
dc_shell> report_timing -path_type full_clock -transition_time -significant_digits 7
****************************************
Report : timing
        -path full_clock
        -delay max
        -max_paths 1
        -transition_time
Design : simple_register
Version: W-2024.09-SP2
Date   : Thu Apr  3 01:41:46 2025
****************************************

Operating Conditions: fast   Library: fast
Wire Load Model Mode: top

  Startpoint: q_reg (rising edge-triggered flip-flop clocked by clk)
  Endpoint: o_reg (rising edge-triggered flip-flop clocked by clk')
  Path Group: clk
  Path Type: max

  Point                         Trans      Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                0.0000000  0.0000000
  clk (in)                   0.8000000 0.0000000  0.0000000 r
  u1/Y (CLKBUFX1)            0.0446310 0.0500520  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/CK (DFFRQX2)         0.0446310 0.0000000  0.0500520 r
  q_reg/Q (DFFRQX2)          0.0173597 0.0859217  0.1359738 r
  o_reg/D (DFFRQX2)          0.0173597 0.0000000  0.1359738 r
  data arrival time                               0.1359738

  clock clk' (rise edge)               5.0000000  5.0000000
  clk (in)                   0.1000000 0.0000000  5.0000000 f
  u1/Y (CLKBUFX1)            0.0234806 0.0424690  5.0424690 f
  U4/Y (CLKINVX1)            0.0144704 0.0131054  5.0555744 r
  o_reg/CK (DFFRQX2)         0.0144704 0.0000000  5.0555744 r
  clock reconvergence pessimism        0.0000000  5.0555744
  o_reg/CK (DFFRQX2)                   0.0000000  5.0555744 r
  library setup time                   -0.0434659 5.0121083
  data required time                              5.0121083
  -----------------------------------------------------------
  data required time                              5.0121083
  data arrival time                               -0.1359738
  -----------------------------------------------------------
  slack (MET)                                     4.8761344