CSC3050 RISC-V Simulator with RVV

CSC3050 Project 3: RISC-V Simulator with RVV

1 Background

RISC-V, an open standard instruction set architecture (ISA), has rapidly become a

pivotal force in academic research and industrial development due to its flexibility

and open-source nature. Unlike proprietary ISAs, RISC-V offers the freedom for

developers to customize and extend the architecture, making it an ideal platform

for innovation in research, education, and the design of specialized hardware. One

of its most impactful extensions is the RISC-V Vector Extension (RVV), which

introduces efficient vector processing capabilities—a cornerstone of modern high performance computing. This is especially critical for applications like machine

learning, cryptography, and scientific simulations, where parallel data processing is

essential for improving computational speed and efficiency.

In this project, you are tasked with extending the QTRVSim RISC-V simulator

to support vector operations by implementing some of the RVV instructions.

After reviewing the number of cycles, you will get a feeling of how this is faster

than conducting element-wise operations.

Start early, this project can be time-consuming if you are not familiar with

simulators.

2 QTRVSim

QTRVSim is a RISC-V CPU simulator for education, where you can try its online

version on this link. Just in case you want to try different instructions, you can refer

to this page: RISC-V Instruction Set Specifications. A helpful video about using

QTRVSim can be found 代写CSC3050  RISC-V Simulator with RVV on Youtube

After familiarizing yourself with the QtRVSim manual, you can begin planning how

to integrate RVV instructions into the existing implementation. The simulator’s

source code, written in C++ and including both the core simulation functions and

graphical user interfaces (GUIs), can be found in the repository at this link. To test

your modifications, QtRVSim offers two methods