牛客网 VL65--状态机与时钟分频

占空比0.25就是4个时钟周期里，一个时钟周期是高电平，其余是低电平。

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;
parameter s3 = 2'b11;

reg [1:0] state;
reg [1:0] next_state;
reg [1:0] cnt;


always@(posedge clk or negedge rst) begin
	if(!rst) 
		state <= 0;
	else
		state <= next_state;

end

always@(*) begin
	case(state)
	  s0: next_state = s1;
	  s1: next_state = s2;
	  s2: next_state = s3;
	  s3: next_state = s0;
	  default: next_state = s0;

	endcase
end

always@(posedge clk or negedge rst) begin
	if(!rst)
		clk_out <= 0;
	else if(next_state == s1)
		clk_out <= 1;
	else
		clk_out <= 0;
end


//*************code***********//
endmodule