Circuits--Sequential --FSM--Serial

1.serial receiver

module top_module(
    input clk,
    input in,
    input reset,
    output done
);

    parameter[3:0] start =4'd0; 
    parameter[3:0] one = 4'd1;
    parameter[3:0] two = 4'd2;
    parameter[3:0] three = 4'd3;
    parameter[3:0] four = 4'd4;
    parameter[3:0] five = 4'd5;
    parameter[3:0] six = 4'd6;
    parameter[3:0] seven = 4'd7;
    parameter[3:0] eight = 4'd8;
    parameter[3:0] stop = 4'd9;
    parameter[3:0] idle = 4'd10;
    parameter[3:0] w = 4'd11;

    reg[3:0] state;
    reg[3:0] next_state;

    always @(*) begin
        case(state)
            start: next_state = one;
            one: next_state = two;
            two: next_state = three;
            three: next_state = four;
            four: next_state = five;
            five: next_state = six;
            six: next_state = seven;
            seven: next_state = eight;
            eight:
                begin
                    if(in)
                        next_state = stop;
                    else
                        next_state = w;
                end
            stop:
                begin
                    if(in)
                        next_state = idle;
                    else
                        next_state = start;
                end
            
            w:
                begin
                    if(in)
                        next_state = idle; 
                    else
                        next_state = w;
                end
            idle:
                begin
                    if(~in)
                        next_state = start;
                    else
                        next_state = idle;
                end
            
        endcase
    end

    always @(posedge clk) begin
        if(reset)
            state <= idle;
        else
            state <= next_state;
    end

    assign done = (state == stop);

endmodule

2. serial datapath

module top_module(
    input clk,
    input reset,
    input in,
    output[7:0] out_byte,
    output done
);

    parameter[3:0] start =4'd0; 
    parameter[3:0] one = 4'd1;
    parameter[3:0] two = 4'd2;
    parameter[3:0] three = 4'd3;
    parameter[3:0] four = 4'd4;
    parameter[3:0] five = 4'd5;
    parameter[3:0] six = 4'd6;
    parameter[3:0] seven = 4'd7;
    parameter[3:0] eight = 4'd8;
    parameter[3:0] stop = 4'd9;
    parameter[3:0] idle = 4'd10;
    parameter[3:0] w = 4'd11;

    reg[3:0] state;
    reg[3:0] next_state;
    reg[7:0] out;

    always @(*) begin
        case(state)
            start:
                begin
                    next_state = one;
                    out[0] = in;
                end

            one: 
                begin
                    next_state = two;
                    out[1] = in;
                end
            two: 
                begin
                    next_state = three;
                    out[2] = in;
                end
            three: 
                begin
                    next_state = four;
                    out[3] = in;
                end
            four: 
                begin
                    next_state = five;
                    out[4] = in;
                end
            five: 
                begin
                    next_state = six;
                    out[5] = in;
                end
            six: 
                begin
                    next_state = seven;
                    out[6] = in;
                end
            seven: 
                begin
                    next_state = eight;
                    out[7] = in;
                end
            eight:
                begin
                    if(in)
                        next_state = stop;
                    else
                        next_state = w;
                end
            stop:
                begin
                    if(in)
                        next_state = idle;
                    else
                        next_state = start;
                end
            
            w:
                begin
                    if(in)
                        next_state = idle; 
                    else
                        next_state = w;
                end
            idle:
                begin
                    if(~in)
                        next_state = start;
                    else
                        next_state = idle;
                end
            
        endcase
    end

    always @(posedge clk) begin
        if(reset)
            state <= idle;
        else
            state <= next_state;
    end

    assign done = (state == stop);
    assign out_byte = (state == stop) ? out : 8'd0;

endmodule

3.Serial checking

module top_module(
    input clk,
    input in,
    input reset,
    output reg[7:0] out_byte,
    output reg done
);
 
    parameter idle = 3'd0;
    parameter start = 3'd1;
    parameter data = 3'd2;
    parameter stop = 3'd3;
    parameter WAIT = 3'd4;
    reg[2:0] state;
    reg[2:0] next_state;
    reg[3:0] counter;
    reg[8:0] data_in;
    reg odd_temp;
    wire isdone;
    always @(*) begin
        case (state)
            idle: 
                begin
                    if(~in) next_state = start;
                    else    next_state = idle;
                end
            start:  next_state = data;
            data:
                begin
                    if(counter == 4'd9)
                        next_state = in ? stop : WAIT;
                    else
                        next_state = data; 
                end
            stop:   next_state = in ? idle : start;
            WAIT:   next_state = in ? idle : WAIT;
 
 
           
        endcase
    end
 
    always @(posedge clk) begin
        if (reset) begin
            state <= idle;
        end
        else state <= next_state;
    end
 
    always @(posedge clk) begin
        if (reset) begin
            done <= 1'd0;
            out_byte <= 8'd0;
            counter <= 4'd0;
        end
        else begin
            case (next_state)
                idle:
                    begin
                        done <= 1'd0;
                        out_byte <= 8'd0;
                        counter <= 4'd0;
                    end 
                start:
                    begin
                        done <= 1'd0;
                        out_byte <= 8'd0;
                        counter <= 4'd0;
                    end
                data:
                    begin
                        done <= 1'd0;
                        out_byte <= 8'd0;
                        counter <= counter + 1'd1;
                        data_in[counter] <= in;
                    end
                stop:
                    begin
                        done <= odd_temp ? 1'd1 : 1'd0;
                        out_byte <= odd_temp ? data_in[7:0] : 8'd0;
                        counter <= 4'd0;
                    end
                WAIT:
                    begin
                        done <= 1'd0;
                        out_byte <= 8'd0;
                        counter <= 4'd0;
                    end
                
            endcase
        end
    end
    assign isdone = (next_state == start);
    parity u0(clk,isdone,in,odd_temp);
endmodule