本文探讨了在IA32架构中，当CR0.PG=1且CR4.PAE=0时，32位分页机制如何将32位线性地址转换为40位物理地址的过程。虽然40位对应于1TB的空间，但线性地址被限制在32位，使得任何给定时刻最多只能访问4GB的线性地址空间。
A logical processor uses 32-bit paging if CR0.PG = 1 and CR4.PAE = 0. 32-bit paging translates 32-bit linear
addresses to 40-bit physical addresses.1 Although 40 bits corresponds to 1 TByte, linear addresses are limited to
32 bits; at most 4 GBytes of linear-address space may be accessed at any given time. -来自IA32文档
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