VCS 多lib 编译， verilog 重命名分开编译

一个大的SOC 系统中经常遇到3方IP 重命名的情况， 有时候改名也不太现实， 所以需要分开编译
j脚本如下

define="ASIC_VERSION  TSMCN12NM "
top_filelist=/xxx/xxxx/xxxx/xxxx/top.f
x1_sys_filelist=/xxx/xxxx/xxxx/xxxx/x1_sys.f
x2_sys_filelist=/xxx/xxxx/xxxx/xxxx/x2_sys.f
x3_sys_filelist=/xxx/xxxx/xxxx/xxxx/x3_sys.f
vlog_log=./com.log
#synopsys_sim.setup 配置
echo '
WORK > DEFAULT
DEFUALT   : ./work
x1_sys_lib  : ./x1_sys_lib
x2_sys_lib  : ./x2_sys_lib
x3_sys_lib  : ./x3_sys_lib
' > synopsys_sim.setup
if [-f $have_vhdl]; then
  echo "xxx_vhdl_lib  : ./vhdl_lib" >> synopsys_sim.setup
fi
#生成top_cfg 用来做lib 的map
echo '
config top_cfg;
  design xxx_soc_top;
  defualt liblist DEFAULT;
  instance xxx_soc_top.u_xxx_subsys.u_xxx_core_0.u_x1_sys_0   liblist   x1_sys_lib ;
  instance xxx_soc_top.u_xxx_subsys.u_xxx_core_0.u_x2_sys_0   liblist   x2_sys_lib ;
  instance xxx_soc_top.u_xxx_subsys.u_xxx_core_0.u_x3_sys_0   liblist   x3_sys_lib ;
endconfig
' > top_cfg.v

## 分开vlogan 编译
vlogan -work x1_sys_lib  -sverilog +v2k -full64 -assert svaext -assert enable_diag -debug_acesss+pp -timescale=1ns/1ps +error+100 +defines+$defines -f $x1_sys_filelist -l $vlog_log -kdb
vlogan -work x2_sys_lib  -sverilog +v2k -full64 -assert svaext -assert enable_diag -debug_acesss+pp -timescale=1ns/1ps +error+100 +defines+$defines -f $x2_sys_filelist -l $vlog_log -kdb
vlogan -work x3_sys_lib  -sverilog +v2k -full64 -assert svaext -assert enable_diag -debug_acesss+pp -timescale=1ns/1ps +error+100 +defines+$defines -f $x3_sys_filelist -l $vlog_log -kdb

vlogan ./top_cfg.v -sverilog +v2k -full64 -assert svaext -assert enable_diag -debug_acesss+pp -timescale=1ns/1ps +error+100 +defines+$defines -f $top_filelist -l $vlog_log -kdb  #默认lib

vcs top_cfg \
   -P ${VCS_HOME}/include/hdl_xmr.tab \
   +line=TFIPC-L +lint=UV \
   -sverilog \
   -full64 \
   -diag macro_values \ 
   -xlrm itf_xmr_hc \
   +warn=noSV-UIP2 +warn=noVNTB \
   -dig timescale \
   +notimingcheck \
   +error+100 |
   -l $logfile \
   -kdb