HDL bits--circuits--sequential logic--more circuits

1.Rule90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            q<={1'b0,q[511:1]}^{q[510:0],1'b0};
    end
endmodule

2.Rule110

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    reg [511:0] c;
    reg [511:0] b;
    reg [511:0] a;
    assign a={1'b0,q[511:1]};
    assign b={q[511:0],1'b0};
    assign c=q;
    always@(posedge clk) begin
        if(load)
            q<=data;
        else
            
        q<=(c&(a^b))|((~c)&a&b)|(c&(~a)&(~b))|(b&(~c)&(~a));
            end
endmodule

3.Conwaylife

这个题目没做出来 先放着吧