Fsm3comb

eachanm

于 2023-08-03 23:30:09 发布

阅读量179

点赞数

分类专栏： HDLBits题目文章标签： verilog

本文链接：https://blog.csdn.net/eachanm/article/details/132094378

版权

HDLBits题目专栏收录该内容

95 篇文章

订阅专栏

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.

Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (), compute the and output () based on the state transition table. statenext_stateout

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: next_state = f(state, in)
    always@ (*) begin
        case (state)
            A: if(in == 1)
                next_state <= B;
            	else 
                next_state <= A;
            B:if(in == 1)
                next_state <= B;
            	else 
                    next_state <= C;
       		C:if(in == 1)
                next_state <= D;
            	else 
                    next_state <= A;
            D:if(in == 1)
                next_state <= B;
            	else 
                    next_state <= C;
            default: next_state <= A;
        endcase
    end
        assign out = state == D ? 1'b1 : 1'b0;
    // Output logic:  out = f(state) for a Moore state machine

endmodule