题目类型：
- 第一部分：企业知识题，建议1分钟作答2题，共10分
- 第二部分：智力题，建议14分钟作答5题，共20分
- 第三部分：技术多选题，建议10分钟作答5题，共15分
- 第四部分：技术单选题，建议10分钟作答10题，共30分
- 第五部分：技术问答题，建议25分钟作答6题，共25分
文章目录
- 企业知识题
- 智力题
- 技术多选题
-
- 1、Which of the fllowing statements are TRUE about "Single-port SRAM, Dual-port SRAM and Two-port SRAM"?( )
- 2、Which of the fllowing statements are TRUE about Timing? ( )
- 3、Which of the fllowing statements are TRUE about low power design? ( )
- 4、In system verilog, which of the following methods can be used by queue? ( )
- 5、Which of the following statements are TRUE about DFT technical? ( )
- 技术单选题
-
- 1、Which is not TRUE about the synchronous clock and asynchronous clock? ( )
- 2、If you need to develop a monitor to sample data from DUT's interface, you will write the sample code to which UVM phase? ( )
- 3、Please choose the logic diagram inside ? block according to the timing waveform( )
- 4、Which of the fllowing options has the correct value of cr?( )
- 5、An asynchronous FIFO with 8bit data width, the FIFO write clock is 100MHz, the read clock is 95MHz, if a data packet size is 4kbit, assuming the inter packet time(the time between two packets) is enough, to avoid data missing, what is the minimum depth of the FIFO?( )
- 6、If only MUX2 is allowed, how many MUX2 is needed at least to implement XOR2 logic? ( )
- 7、Which one is the correct weight distribution of src and dst?
- 8、Which interface below is not belong to SERDES?( )
- 9、We have several task in module tb. Which print is the expect result ? ( )
- 10、When a circuit is implemented by Verilog code, which level code is most used? ( )
- 技术问答题
-
- 1、Read below timing report and answer question. (8 scores)
-
- 1.1 What's the type of the timing path? For example, Hold timing path. (1 scores)
- 1.2 What's the number of clock“cIk" period, uncertainty value and skew value? (3 scores)
- 1.3 Does this path meet the timing requirement? If not, please list the main reasons of the timing violation and methods to fx the timing violation. (4 scores)
- 2、Please write Verilog code to implement rising-edge detect using asynchronous reset and synchronous reset. The input signal is: sig_a, clk, rst_n, output signal is: sig_b. (6 scores)
- 3、As we know, handshake is a way to make sure data crrectly transfer through pipeline. It constructs of valid, ready/acknowledge signal and data to betransferred. Please design one handshake delay method, in which combinational logic of valid and acknowledge signal are parted by fip-fop respectively to improve timing. (6 scores)
- 4、What is RAW (read-after-write hazard) in CPU? (1 scores) Is there any way to solve the read-after-write hazard? Try to list 2 of them. (2 scores*2 = 4 scores)
企业知识题
知识点补充
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