opensbi

Minimal implementation of a time-sharing kernel on RISC-V, implemented in Zig, on top of OpenSBI

Trivial RISC-V Linux binary bootloader

Linux 7.2 on the ESP32-S31 (RV32, 16 MiB PSRAM): OpenSBI, LCD console, Wi-Fi, USB and a microSD root. Ready-to-flash releases and a guide to the SoC internals.

Uotan RISC-V Emulator: Towards a Compliant and Educational Full-System RISC-V Emulator

A RISCV32IMAC Emulator

RISC-V emulator for Web written in Go/WebAssembly. It supports OpenSBI, Linux, virtio, and diagnostics. feat. GPT-5.5

RV64GC RISC-V emulator written in Go capable of booting Linux, NetBSD, FreeBSD, and OpenBSD with OpenSBI, U-Boot, SV39 virtual memory, and VirtIO devices.

my progress and contribution yocto project in tessolve

MatteOS: The educational OS for RISC-V

RISC-V64 SMP OS in C (reimplemented from rCore's Rust design). 7+1 hart split with OpenSBI domains; bidirectional PMP denial verified by fault probes, not assumed.

Action that automatically builds the latest VisionFive 2 firmware (OpenSBI + U-Boot), for personal use.

RISC-V BootFlow Playgroun on QEMU

64-bit RISC-V SoC v.0.1.0

Example of how to write a baremetal Rust program for RV64 which is booted by OpenSBI.

Three RV32 CPU profiles: 5-stage performance, Sv32/Linux system, and 2-wide OoO, with Verilator/NEMU verification and Nangate45 academic ASIC evidence.

xv6-signal-handling: POSIX-style signal implementation for xv6 kernel - SUSTech project of CS302: Operating Systems in Spring 2025 - Score: 100/100

Low-level I/O systems: OpenSBI, bare-metal C, Linux drivers.

A minimal RISC-V 64-bit OS kernel written in Odin, using OpenSBI.

Implementing the “OS in 1,000 Lines” tutorial in Zig