data-forwarding

Sensor Data Forwarding, Arduino Uno, ROS1, Ubuntu

Cycle-accurate 5-stage MIPS pipeline simulator in C++ (IF/ID/EX/MEM/WB) with hazard detection + forwarding. Includes per-cycle state tracking and regression tests/traces for correctness.

5-stage pipelined 32-bit MIPS processor

A Python-based simulator for a 5-stage MIPS pipeline with hazard detection, forwarding, and branch handling.

Browser-based 5-stage MIPS pipeline simulator. Visualizes RAW, Load-Use, Control, Structural & Cache hazards in real time. Toggle forwarding and branch prediction, compare CPI instantly.

Final Project for CMPEN 331: This is a 5-stage pipelined MIPS-style processor datapath written in Verilog, with hazard detection, data forwarding, instruction and data memory, and support for a small subset of MIPS instructions (lw, sw, add, sub). The code that I wrote is contained within datapath.v

5-stage in-order pipeline simulator in C: IF/ID/EX/MEM/WB stages, custom 11-opcode ISA, load-use stall detection, EX/MEM and MEM/WB data forwarding, 2-cycle branch/jump flush. Direct-mapped icache and dcache (64 lines, 4-cycle miss). Outputs cycle-by-cycle latch state, timing diagrams, CPI and cache stats.

Notification listener, webhook triggers.

5-stage MIPS pipeline CPU in Verilog with data forwarding, hazard detection and full instruction set. Simulated on EDA Playground.

RISC-V 3 stage in-order pipeline in verilog

A 5-stage pipelined RISC processor implemented in VHDL, featuring fetch, decode, execute, memory, and writeback stages. Includes a Python-based assembler, hazard detection, data forwarding, branch prediction, and a comprehensive testbench suite.

32-bit pipelined RISC-V processor implemented in Verilog with hazard detection, data forwarding, and FPGA deployment

Python library for forwarding Pretix data to webhooks, external systems and other Pretix systems