analog-computing

Scalable HW-Aware Training for Analog In-Memory Computing

A Recursive Ontological Framework for Cognitive Design, Neurodivergence Modeling, AI Co-Development, and "Structural AI"

IHP26a TinyTapeout implementation of a RISC-V CPU with an integrated SRAM-based compute-in-memory (CIM) accelerator for performing efficient analog matrix multiplications.

Differentiable Analog Neural Network Simulation — from PyTorch to SPICE. 77.58% Fashion-MNIST, 42/42 SPICE match, scaling law R²=0.9385

Falsifiable engineering specs (Modules A–G) for the LifeNode Processual architecture: bio-electric & MOF transduction, NV-diamond Q-Core, Physarum biohybrid interface, ASCALON phase filter, Living Walls. Theory on Zenodo. No product — validation or falsification only. CC-BY-NC-SA 4.0. Technology adapts to Life's rhythm, not the reverse.

A Python-based interactive museum simulation engine for the historical Rheinmetall Kommandogerat-58 fire control computer and 5.5 cm Gerat 58 cannon. This system models deterministic 3D ballistic cam geometry, 16-cable electrical grid states, pneumatic loading cycles, and active thermal radar cooling.

A programming language for wave-based phononic processors. Computation as resonance, memory as sustained oscillation, control flow as phase gating—designed from acoustic physics, not transistor assumptions.

Hardware-agnostic AI compiler suite. Compile GGUF, ONNX, PyTorch, and SafeTensors models onto FPGAs, analog circuits, MCU swarms, photonic MZI meshes, neuromorphic chips, and CIM accelerators — not GPUs. Includes SiL emulator, real-time dashboard, federated learning, and carbon-aware compilation.

Two brains on one analog substrate from ~80% unsupervised SCFF bulk + ~20% closed-form SLDA namer: the math model for a forward-only, on-chip continual learner. Behavioral simulation, no silicon. Draft 6.0 = the "baby neocortex," validated across 11 phases.

Behavioral analog matrix-multiplication model, driver contract, reproducible receipts, and open-silicon roadmap.

An open analog-circuit learning competition: recognize MNIST in SPICE and compare accuracy with energy.

End-to-end optical neural network: trained MNIST weights → dithered binary photomask (GDSII) → 3D ray-traced optical MVM → validation. Binary quantization costs only 0.42pp accuracy (89.9% → 89.5%).

HeteroCore component: analog crossbar noise, precision, and drift simulator

Analog Robustness CI — will your AI model survive analog hardware? Break-even economics + noise/drift/ADC robustness simulation for AIMC and photonic accelerators.

Domain-specific language for hybrid analog-digital programming, designed to bring structure and abstraction to analog computation and hybrid systems.

面向模拟存算一体硬件的 AI 二阶训练研究框架，通过 K-FAC、矩阵自由 GGN 和残差门控 Krylov 校正，在避免显式构造雅可比矩阵的同时，将大规模曲率求解映射到非理想模拟阵列。

Hardware-aware S4D state-space models on simulated analog memristor crossbars: a reproducible neuromorphic in-memory computing co-design study (PyTorch, CPU-only).

Лаборатория и библиотека симуляций аналоговых и нейроморфных процессоров. Чертежи, математические модели и Python-скрипты нелинейных вычислительных ядер на транзисторах, мемристорах и ОУ. База прототипов для будущего физического воплощения в железе (In-Materio Physical Computing) вне архитектуры Фон Неймана.

Differential memristive crossbar with a hardware-friendly in-situ (Manhattan/sign-rule) learning rule, tested on parity-3 — the calibrated in-memory-compute baseline of the physical-learning-substrates portfolio. Verdict #1: PASS, learns parity-3 at SNR ~24.5 (half co-located: physics activations, off-array error sign, physical-pulse increment).

Radiative Cooling