This is an extensible Python-based framework for the automated generation of synthesis-ready HDL code from high-level finite-state machine (FSM) specifications. It supports configurable generation of Verilog-2005 and VHDL-2008 implementations.
- Finite-state machines (FSMs) are accepted as state-transition tables in KISS2 or JSON format.
- Generate clean, synthesis-ready Verilog-2005 and VHDL-2008 code.
- Output configuration is adjustable using user-defined parameters, enabling multiple distinct HDL implementations from the same FSM specification.
- Both a command-line interface (CLI) and programmatic usage are available.
- The framework uses an explicit internal FSM data model implemented with Python data classes.
- Its modular and extensible design allows additional parameters and functionality to be added without altering the core engine.
- The framework was validated on standard FSM benchmarks.
- Generated HDL was checked through syntax analysis.
- Behavioral correctness was confirmed through simulation with full state and transition coverage.
- Generated designs were evaluated through FPGA synthesis and implementation toolflows.
- Runtime and memory usage were measured to confirm practical overhead.
Note
To avoid having to manually compile any tools that are not available in your distribution or on your platform, it is strongly recommended that you use the OSS CAD Suite.
Clone the repository and change into the directory:
git clone https://github.com/drifter1/fsm2hdl.git
cd fsm2hdl
To build using hatch type:
make build
To install in a hatch environment locally:
make install
To run the included pytest tests type make test.
To lint and format the source code using hatch type make lint and make format, respectively.
To generate the documentation using pdoc type make docs.
Perform cleanup with make clean.
The included benchmarks stem from the well-regarded MCNC91 benchmark collection.
All rights reserved by the owners.
S. Yang 1991. Logic Synthesis and Optimization Benchmarks User Guide: Version 3.0, Microelectronics Center of North Carolina (MCNC) Research Triangle Park, NC, USA.
The tool can be evaluated using the included benchmarks with the following Make targets:
| Evaluation step | Description | Command |
|---|---|---|
| HDL generation | Generate HDL code for the included FSM benchmarks. | make hdl |
| Syntax checking | Check the generated HDL for syntax errors. | make syntax |
| Functional simulation | Simulate the generated HDL to verify functional behavior. | make sim |
| FPGA synthesis and implementation | Run FPGA synthesis and implementation flows. | make synth |
| Performance and resource footprint | Measure runtime, peak memory usage, and file utilization. | make perf |
fsm2hdl is released under the MIT license. You are permitted to use, modify, and distribute fsm2hdl, under the condition that all copies of the software include a copy of the copyright notice and license terms.
TBD